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sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110 japan overview the LC78625e is a cmos lsi that implements the signal processing and servo control required by compact disc players, laser discs, cd-v, cd-i and related products. the LC78625e provides several types of signal processing, including demodulation of the optical pickup efm signal, de-interleaving, error detection and correction, and digital filters that can help reduce the cost of cd player units. it also processes a rich set of servo system commands sent from the control microprocessor. it also incorporates an efm-pll circuit and a one-bit d/a converter. this lsi is an improved version of the lc78620e. in addition to supporting low-voltage operation, on/off control of the de-emphasis function and use of the bilingual function have been enabled in certain additional modes. functions the LC78625e takes an hf signal as input, digitizes (slices) that signal at a precise level, converts that signal to an efm signal, and generates a pll clock with an average frequency of 4.3218 mhz by comparing the phases of that signal and an internal vco. a precise reference clock and the necessary internal timings are generated using an external 16.9344 mhz crystal oscillator. disc motor speed control using a frame phase difference signal generated from the playback clock and the reference clock frame synchronization signal detection, protection, and interpolation to assure stable data readout efm signal demodulation and conversion to 8-bit symbol data subcode data separation from the efm demodulated signal and output of that data to an external microprocessor subcode q signal output (lsb first) to a microprocessor over the serial interface after performing a crc error check demodulated efm signal buffering in internal ram to handle up to ? frames of disc rotational jitter demodulated efm signal reordering in the prescribed order for data unscrambling and de-interleaving error detection, correction, and flag processing (error correction scheme: dual c1 plus dual c2 correction) the LC78625e sets the c2 flags based on the c1 flags and a c2 check, and then performs signal interpolation or muting depending on the c2 flags. the interpolation circuit uses a quadruple interpolation scheme. the output value converges to the muting level when four or more consecutive c2 flags occur. package dimensions unit: mm 3174-qfp80e sanyo: qfp80e [LC78625e] cmos lsi ordering number : en5502 22897ha (ot) no. 5502-1/35 LC78625e sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110 japan compact disc player dsp
support for command input from a control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8-bit serial input) built-in digital output circuits. arbitrary track counting to support high-speed data access d/a converter outputs with data continuity improved by 8 oversampling digital filters. (these filters function as 4 oversampling filters during double-speed playback.) built-in ? d/a converter implemented by a third-order noise shaper circuit (for pwm output) built-in digital attenuator (8 bits - alpha, 239 steps) built-in digital de-emphasis circuit that can be controlled externally in some modes zero-cross muting support for 2 -speed dubbing support for bilingual applications general-purpose i/o ports: 4 pins (when the antishock mode is turned off) features 5 v single-voltage power supply low-voltage operation: can be operated at 3.3 v 10% (at normal playback speed) 80-pin qfp package equivalent circuit block diagram no. 5502- 2 /35 LC78625e
pin assignment no. 5502- 3 /35 LC78625e parameter symbol conditions ratings unit maximum supply voltage v dd max v ss ?0.3 to +7.0 v maximum input voltage v in v ss ?0.3 to v dd + 0.3 v maximum output voltage v out v ss ?0.3 to v dd + 0.3 v allowable power dissipation pd max 300 mw operating temperature topr ?0 to +75 c storage temperature tstg ?0 to +125 c specifications absolute maximum ratings at ta = 25 c, v ss = 0 v parameter symbol conditions ratings unit min typ max v dd (1) v dd , xv dd , lv dd , rv dd , vv dd : 3.0 5.5 v supply voltage at normal playback speed v dd (2) v dd , xv dd , lv dd , rv dd , vv dd : 4.5 5.5 v at 2 playback speed defi, fzd, asdack/p0, asfin/p1, v ih (1) asdepc/p2, aslrck/p3, coin, res, hfl, 0.7 v dd v dd v input high-level voltage tes, sbck, rwc, cqck, tai, test1 to test5, demo, cs v ih (2) efmin 0.6 v dd v dd v defi, fzd, asdack/p0, asfin/p1, v il (1) asdepc/p2, aslrck/p3, coin, res, hfl, 0 0.3 v dd v input low-level voltage tes, sbck, rwc, cqck, tai, test1 to test5, demo, cs v il (2) efmin 0 0.4 v dd v data setup time t su coin, rwc : figure 1 400 ns data hold time t hd coin, rwc : figure 1 400 ns high-level clock pulse width t wh sbck, cqck : figuires 1, 2 and 3 400 ns low-level clock pulse width t wl sbck, cqck : figuires 1, 2 and 3 400 ns data read access time t rac sqout, pw : figuires 2 and 3 0 400 ns allowable operating ranges at ta = 25 c, v ss = 0 v continued on next page.
no. 5502- 4 /35 LC78625e continued from preceding page. note: for guaranteed operation, the vco oscillator frequency range adjustment resistor fr must be a 1.20 k 5.0% tolerance resistor. parameter symbol conditions ratings unit min typ max command transfer time t rwc rwc : figure 1 1000 ns subcode q read enable time t sqe wrq: figure 2, with no rwc signal 11.2 ms subcode read cycle t sc sfsy : figure 3 136 s subcode read enable time t se sfsy : figure 3 400 ns port input data setup time t psu asdack/p0, asfin/p1, asdepc/p2, 400 ns aslrck/p3, rwc : figure 4 port input data hold time t phd asdack/p0, asfin/p1, asdepc/p2, 400 ns aslrck/p3, rwc : figure 4 port input clock setup time t rcq cqck, rwc : figure 4 100 ns port output data delay time t pdd asdack/p0, asfin/p1, asdepc/p2, 1200 ns aslrck/p3, rwc : figure 5 input level v in (1) efmin 1.0 vp-p v in (2) xin : capacitor coupled input 1.0 vp-p operating frequency range f op (1) efmin 10 mhz crystal oscillator frequency f x xin, xout : in 16m mode 16.9344 mhz parameter symbol conditions ratings unit min typ max current drain i dd 30 45 ma defi, efmin, fzd, asdack/p0, asfin/p1, i ih (1) asdepc/p2, aslrck/p3, coin, res, hfl, 5 a input high-level current tes, sbck, rwc, cqck : v in = 5 v i ih (2) tai, test1 to test5, demo, cs : 25 75 a v in = v dd = 5.5 v defi, efmin, fzd, asdack/p0, asfin/p1, input low-level current i il asdepc/p2, aslrck/p3, coin, res, hfl, ? a tes, sbck, rwc, cqck, tai, test1 to test5, demo, cs : v in = 0 v efmo, efmo, clv + , clv , v/p, focs, v oh (1) pck, fseq, toff, tgl, thld, jp + , jp , 4 v emph, eflg, fsx : i oh = ? ma mutel, muter, lrcko, dforo, dfolo, dacko, tst10, asdack/p0, asfin/p1, v oh (2) asdepc/p2, aslrck/p3, lrsy, ck2, 4 v output high-level voltage romxa, c2f, sbsy, pw, sfsy, wrq, sqout, tst11, 16m, 4.2m, cont : i oh = ?.5 ma v oh (3) laser : i oh = ? ma 4.6 v v oh (4) dout : i oh = ?2 ma 4.5 v v oh (5) lchp, rchp, lchn, rchn : i oh = ? ma 3.0 4.5 v efmo, efmo, clv + , clv , v/p, focs, v ol (1) pck, fseq, toff, tgl, thld, jp + , jp , 1 v emph, eflg, fsx : i ol = 1 ma mutel, muter, lrcko, dforo, dfolo, dacko, tst10, asdack/p0, asfin/p1, v ol (2) asdepc/p2, aslrck/p3, lrsy, ck2, 0.4 v output low-level voltage romxa, c2f, sbsy, pw, sfsy, wrq, sqout, tst11, 16m, 4.2m, cont, laser : i ol = 2 ma v ol (3) dout : i ol = 12 ma 0.5 v v ol (4) fst : i ol = 5 ma 0.75 v v ol (5) lchp, rchp, lchn, rchn : i ol = 1 ma 0.5 2.0 v i off (1) pdo, clv + , clv , jp + , jp , fst : 5 a output off leakage current v out = 5 v i off (2) pdo, clv + , clv , jp + , jp : v out = 0 v ? a charge pump output current i pdoh pdo : riset = 68 k 100 125 150 a i pdol pdo : riset = 68 k ?50 ?25 ?00 a electrical characteristics at ta = 25 c, v dd = 5 v, v ss = 0 v
no. 5502- 5 /35 LC78625e parameter symbol conditions ratings unit min typ max lchp, rchp, lchn, rchn; total harmonic distortion thd + n 1 khz: 0 db data input, using the 20 khz 0.008 0.0010 % low-pass filter (ad725d built in) lchp, rchp, lchn, rchn; dynamic range dr 1 khz: ?0 db data input, using the 20 khz 84 88 db low-pass filter and the a filter (ad725d built in) lchp, rchp, lchn, rchn; signal-to-noise ratio s/n 1 khz: 0 db data input, using the 20 khz 98 100 db low-pass filter and the a filter (ad725d built in) lchp, rchp, lchn, rchn; crosstalk ct 1 khz: 0 db data input, using the 20 khz 96 98 db low-pass filter (ad725d built in) one-bit d/a converter analog characteristics at ta = 25 c, v dd = lv dd = rv dd = 5 v, v ss = lv ss = rv ss = 0 v figure 1 command input figure 2 subcode q output figure 3 subcode output note: measured with the normal-speed playback mode digital attenuator in the sanyo one-bit d/a converter block reference circui t.
figure 4 general-purpose port input timing figure 5 general-purpose port output timing no. 5502- 6 /35 LC78625e
one-bit d/a converter output block reference circuit no. 5502- 7 /35 LC78625e
pin functions no. 5502- 8 /35 LC78625e pin no. symbol i/o function 1 defi i defect detection signal (def) input (this pin must be connected to 0 v if unused.) 2 tai i test input. a pull-down resistor is built in. (this pin must be connected to 0 v in normal operation.) 3 pdo o external vco control phase comparator output 4 vv ss pll pins internal vco ground. (this pin must be connected to 0 v.) 5 iset ai pdo output current adjustment resistor connection 6 vv dd internal vco power supply. 7 fr ai vco frequency range adjustment 8 v ss digital system ground. (this pin must be connected to 0 v.) 9 efmo o efm signal inverted output 10 efmo o slice level control efm signal output 11 efmin i efm signal input 12 test2 i test input. a pull-down resistor is built in. this pin must be connected to 0 v in normal operation. 13 clv + o spindle servo control output. acceleration when clv+ is high, deceleration when clv- is high. 14 clv o three-value output is also possible when specified by microprocessor command. 15 v/p o rough servo/phase control automatic switching monitor output. outputs a high level during rough servo and a low level during phase control. 16 focs o focus servo on/off output. focus servo is on when the output is low. 17 fst o focus start pulse output. this is an open-drain output. 18 fzd i focus error zero cross signal input. (this pin must be connected to 0 v if unused.) 19 hfl i track detection signal input. this is a schmitt input. 20 tes i tracking error signal input. this is a schmitt input. 21 pck o efm data playback clock monitor. outputs 4.3218 mhz when the phase is locked. 22 fseq o synchronization signal detection output. outputs a high level when the synchronization signal detected from the efm signal and the internally generated synchronization signal agree. 23 toff o tracking off output 24 tgl o tracking gain switching output. increase the gain when low. 25 thld o tracking hold output 26 test3 i test input. a pull-down resistor is built in. (this pin must be connected to 0 v.) 27 v dd digital system power supply. 28 jp + o track jump output. a high level output from jp+ indicates acceleration during an outward jump or deceleration during an inward jump. 29 jp o a high level output from jp- indicates acceleration during an inward jump or deceleration during an outward jump. three-value output is also possible when specified by microprocessor command. 30 demo i sound output function input used for end product adjustment manufacturing steps. a pull-down resistor is built in. (this pin mu st be connected to 0 v.) 31 test4 i test input. a pull-down resistor is built in. (this pin must be connected to 0 v.) 32 emph o de-emphasis monitor pin. a high level indicates playback of a de-emphasis disk. 33 lrcko o word clock output 34 dforo o digital filter outputs right channel data output 35 dfolo o left channel data output 36 dacko o bit clock output 37 tst10 o test output. leave open. (normally outputs a low level.) continued on next page.
no. 5502- 9 /35 LC78625e continued from preceding page. pin no. symbol i/o function 38 asdack/p0 i/o bit clock input 39 asdfin/p1 i/o left and right channel data input 40 asdepc/p2 i/o sets the built-in de-emphasis filter on or off. (high: on, low: off) 41 aslrck/p3 i/o l/r clock input 42 lrsy o l/r clock output 43 ck2 o bit clock output inverted polarity clock output romxa application output signals (after reset) (during ck2con mode) 44 romxa o interpolation data output rom data output (during romxa mode) (after reset) 45 c2f o c2 flag output 46 mutel o left channel mute output 47 lv dd left channel power supply 48 lchp o left channel p output 49 lchn o left channel n output 50 lv ss one-bit d/a converter signals left channel ground. must be connected to 0 v. 51 rv ss right channel ground. must be connected to 0 v. 52 rchn o right channel n output 53 rchp o right channel p output 54 rv dd right channel power supply 55 muter o right channel mute output 56 dout o digital output 57 sbsy o subcode block synchronization signal output 58 eflg o c1, c2, single and double error correction monitor pin 59 pw o subcode p, q, r, s, t, u and w output 60 sfsy o subcode frame synchronization signal output. this signal falls when the subcodes are in the standby state. 61 sbck i subcode readout clock input. this is a schmitt input. (this pin must be connected to 0 v if unused.) 62 fsx o output for the 7.35 khz synchronization signal divided from the crystal oscillator 63 wrq o subcode q output standby output 64 rwc i read/write control input. this is a schmitt input. 65 sqout o subcode q output 66 coin i command input from the control microprocessor 67 cqck i input for the command input acquisition clock or the sqout pin subcode readout clock input. this is a schmitt input. 68 res i reset input. this pin must be set low briefly after power is first applied. 69 tst11 o test output. leave open. (normally outputs a low level.) 70 laser o laser on/off output. controlled by serial data commands from the control microprocessor. 71 16m o 16.9344 mhz output 72 4.2m o 4.2336 mhz output 73 cont o supplementary control output. controlled by serial data commands from the control microprocessor. 74 test5 i test input. a pull-down resistor is built in. (this pin must be connected to 0 v.) 75 cs i chip select input. a pull-down resistor is built in. this pin must be connected to 0 v if unused. 76 xv ss crystal oscillator ground. must be connected to 0 v. 77 xin i connections for a 16.9344 mhz crystal oscillator 78 xout o 79 xv dd crystal oscillator power supply 80 test1 i test input. a pull-down resistor is built in. (this pin must be connected to 0 v.) ? when antishock mode is not used, these pins are used as general- purpose i/o ports (p0 to p3). t hey must either be set to input mode and connected to 0 v, or set to output mode and left open, if unused. the antishock inputs in antishock mode. note: all power-supply pins (v dd , vv dd , lv dd , rv dd , and xv dd ) must be connected to the same potential.
cd system block diagrams pin applications 1. hf signal input circuit; pin 11: efmin, pin 10: efmo, pin 9: efmo, pin 1: defi, pin 13: clv + an efm signal (nrz) sliced at an optimal level can be acquired by inputting the hf signal to efmin. the LC78625e handles defects as follows. when a high level is input to the defi pin (pin 1), the efmo (pin 9) and efmo (pin 10) pins (the slice level control outputs) go to the high-impedance state, and the slice level is held. however, note that this function is only valid in clv phase control mode, that is, when the v/p pin (pin 15) is low. this function can be used in combination with the la9230/40 series def pin. note: if the efmin and clv+ signal lines are too close to each other, unwanted adiation can result in error rate degradation. we recommend laying a ground or v dd shield line between these two lines. 2. pll clock generation circuit; pin 3: pdo, pin 5: iset, pin 7: fr, pin 21: pck since the LC78625e includes a vco circuit, a pll circuit can be formed by connecting an external rc circuit. iset is the charge pump reference current, pdo is the vco circuit loop filter, and fr is a resistor that determines the vco frequency range. (reference values) r1 = 68 k , c1 = 0.1 f r2 = 680 k , c2 = 0.1 f r3 = 1.2 k note: we recommend using a 5.0% tolerance carbon film resistor for r3. no. 5502- 10 /35 LC78625e
no. 5502- 11 /35 LC78625e 3. vco monitor; pin 21: pck pck is a monitor pin that outputs an average frequency of 4.3218 mhz, which is the vco frequency divided by two. 4. synchronization detection monitor; pin 22: fseq pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the efm signal read in by pck and the timing generated by the counter (the interpolation synchronization signal) agree. this pin is thus a synchronization detection monitor. (it is held high for a single frame.) 5. servo command function; pin 64: rwc, pin 66: coin, pin 67: cqck commands can be executed by setting rwc high and inputting commands to the coin pin in synchronization with the cqck clock. note that commands are executed on the falling edge of rwc. focus start track jump muting control one byte commands disc motor control miscellaneous control track check two-byte command (rwc set twice) digital attenuator two-byte commands (rwc set once) general-purpose port i/o data setup one-byte commands two-byte commands (rwc set twice) two-byte commands (rwc set once)
command noise rejection this command reduces the noise on the cqck clock signal. while this is effective for noise pulses shorter than 500 ns, the cqck timings t wl , t wh , and t su (see page 5, figures 1 and 2), must be set to be at least 1 s. no. 5502- 12 /35 LC78625e code command res = l $ef command input noise reduction mode $ee reset the above mode. l l 6. focus servo circuit; pin 16: focs, pin 17: fst, pin 18: fzd, pin 70: laser code command res = l $08 focus start #1 $a2 focus start #2 $0a laser on $8a laser off l l $fe nothing the focs, fst, and fzd pins are not required when the LC78625e is used in combination with an la9230/40 series lsi. fzd should be connected to 0 v when these pins are not used. the la9230/40 series focus start command is identical to the LC78625e focus start #1 command. nothing this command can be used to initialize the LC78625e by inputting fe (hexadecimal: hexadecimal constants are written with a dollar sign ($) prefix). note that $00 is the reset command for the la9230/40 series, and should be used with care since it clears the result of the automatic adjustment process and returns these chips to their initial states. laser control the laser pin can be use as an extended output port. focus start when the LC78625e is used in combination with an la9230/40 series lsi, the focus start operation is executed completely on the servo side by commands from the control microprocessor. the following section describes this operation when the LC78625e is used in combination with an la9210m or la9211m. when a focus start instruction (either focus start #1 or focus start #2) is input as a servo command, first the charge on capacitor c1 is discharged by fst and the objective lens is lowered. next, the capacitor is charged by focs, and the lens is slowly raised. fzd falls when the lens reaches the focus point. when this signal is received, focs is reset and the focus servo turns on. after sending the command, the microprocessor should check the in-focus detection signal (the la9210 drf signal) to confirm focus before proceeding to the next part of the program. if focus is not achieved by the time c1 is fully charged, the microprocessor should issue another focus command and iterate the focus servo operation.
note: * values in parentheses are for the focus start #2 command. the only difference is in the fst low period. * an fzd falling edge will not be accepted during the period that fst is low. * after issuing a focus start command, initialization will be performed if rwc is set high. therefore, do not issue the next comm and during focus start until the focus coil drive s curve has completed. * when focus cannot be achieved (i.e., when fzd does not go low) the focs signal will remain in the high state and the lens will remain raised, so the microprocessor should initialize the system by issuing a nothing command. * when the res pin is set low, the laser pin is set high directly. * focus start using the demo pin executes a mode #1 focus start. no. 5502- 13 /35 LC78625e
no. 5502- 14 /35 LC78625e 7. clv servo circuit; pin 13: clv + , pin 14: clv , pin 15: v/p the clv + pin provides the signal that accelerates the disk in the forward direction and the clv pin provides the signal that decelerates the disk. commands from the control microprocessor select one of the four modes accelerate, decelerate, clv and stop. the table below lists the clv + and clv outputs in each of these modes. code command res = l $04 disc motor start (accelerate) $05 disc motor clv (clv) $06 disc motor brake (decelerate) $07 disc motor stop (stop) l l mode clv + clv accelerate h l decelerate l h clv pulse output pulse output stop l l internal mode clv + clv v/p rough servo (when determined to be under speed) h l h rough servo (when determined to be over speed) l h h phase control (pck locked) pwm pwm l note: * clv servo control commands can set the toff pin low only in clv mode. that pin will be at the high level at all other times. co ntrol of the toff pin by microprocessor command is only valid in clv mode. clv mode in clv mode the LC78625e detects the disk speed from the hf signal and provides proper linear speed using several different control schemes by switching the dsp internal modes. the pwm period corresponds to a frequency of 7.35 khz. the v/p pin outputs a high level during rough servo and a low level during phase control. rough servo gain switching for 8 cm discs, the rough servo mode clv control gain can be set about 8.5 db lower than the gain used for 12 cm discs. code command res = l $a8 disc 8 set $a9 disc 12 set l l
no. 5502- 15 /35 LC78625e phase control gain switching the phase control gain can be changed by changing the divisor used by the dividers in the stage immediately preceding the phase comparator. code command res = l $b1 clv phase comparator divisor: 1/2 $b2 clv phase comparator divisor: 1/4 $b3 clv phase comparator divisor: 1/8 $b0 no clv phase comparator divisor used l l clv three-value output the clv three-value output command allows the clv to be controlled by a single pin. however, the spindle gain is 6 db lower when this pin is used, so applications must increase the gain in the servo system. code command res = l $b4 clv three-value output $b5 clv two-value output (the scheme used by previous products) l l
no. 5502- 16 /35 LC78625e internal brake modes code command res = l $c5 internal brake on $c4 internal brake off l l $a3 internal brake cont $cb internal brake continuous mode $ca reset continuous mode l l $cd ton mode during internal braking $cc reset ton mode l l issuing the internal brake on command ($c5) sets the LC78625e to internal brake mode. in this mode, the disc deceleration state can be monitored from the wrq pin when a brake command ($06) is executed. in this mode the disc deceleration state is determined by counting the efm signal density in a single frame, and when the efm signal count falls under four, the clv pin is dropped to low. at the same time the wrq signal, which functions as a brake completion monitor, goes high. when the microprocessor detects a high level on the wrq signal, it should issue a stop command to fully stop the disc. in internal brake continuous mode, the clv pin high-level output braking operation continues even after the wrq brake completion monitor goes high. note that if errors occur in deceleration state determination due to noise in the efm signal, the problem can be rectified by changing the efm signal count from four to eight with the internal brake control command ($a3). in internal braking ton mode, the toff pin is held low during internal brake operations. we recommend using this feature, since it is effective at preventing incorrect detection at the disc mirror surface. note: if focus is lost during the execution of an internal brake command, the pickup must first be refocussed and then the internal b rake command must be reissued. since incorrect deceleration state determination is possible depending on the efm signal playback state (e.g., disc defects, ac cess in progress), we recommend using these functions in combination with a microprocessor. 8. track jump circuit; pin 19: hfl, pin 20: tes, pin 23: toff, pin 24: tgl, pin 25: thld, pin 28: jp + , pin 29: jp the LC78625e supports the two track count modes listed below. the earlier track count function uses the tes signal directly as the internal track counter clock. to reduce counting errors resulting from noise on the rising and falling edges of the tes signal, the new track count function prevents noise induced errors by using the combination of the tes and hfl signals, and implements a more reliable track count function. however, dirt and scratches on the disc can result in hfl signal dropouts that may result in missing track count pulses. thus care is required when using this function. code command res = l $22 new track count mode (using the tes/hfl combination) l l $23 previous track count mode (directly counts the tes signal)
no. 5502- 17 /35 LC78625e tj commands when the LC78625e receives a track jump instruction as a servo command, it first generates accelerating pulses (period a) and next generates deceleration pulses (period b). the passage of the braking period (period c) completes the specified jump. during the braking period, the LC78625e detects the beam slip direction from the tes and hfl inputs. toff is used to cut the components in the te signal that aggravate slip. the jump destination track is captured by increasing the servo gain with tgl. in thld period toff output mode the toff signal is held high during the period when thld is high. note: of the modes related to disc motor control, the toff pin only goes low in clv mode, and will be high during start, stop, and brake operations. note that the toff pin can be turned on and off independently by microprocessor issued commands. however, this function is only valid when disc motor control is in clv mode. code command res = l $a0 previous track jump l l $a1 new track jump $11 1 track jump in #1 $12 1 track jump in #2 $31 1 track jump in #3 $52 1 track jump in #4 $10 2 track jump in $13 4 track jump in $14 16 track jump in $30 32 track jump in $15 64 track jump in $17 128 track jump in $19 1 track jump out #1 $1a 1 track jump out #2 $39 1 track jump out #3 $5a 1 track jump out #4 $18 2 track jump out $1b 4 track jump out $1c 16 track jump out $38 32 track jump out $1d 64 track jump out $1f 128 track jump out $16 256 track check $0f toff $8f ton l l $8c track jump brake $21 thld period toff output mode $20 reset thld period toff output mode l l
no. 5502- 18 /35 LC78625e track jump modes the table lists the relationships between acceleration pulses, deceleration pulses, and the braking period. note : * applications can select whether or not a braking period (period c) is present. code $f6 selects operation without a braking per iod, and code $7f selects operation with a 60-ms braking period. the LC78625e defaults to no braking period operation after a reset. * as indicated in the table, actuator signals are not output during the 256 track check function. this is a mode in which the tes signal is counted in the tracking loop off state. therefore, feed motor forwarding is required. * the servo command register is automatically reset after one cycle of the track jump sequence (a, b, c) completes. * if another track jump command is issued during a track jump operation, the contents of that new command will be executed immedi ately. * the 1 track jump #3 and 2 track jump modes (the earlier modes) do not have a braking period (the c period). since brake mode mu st be generated by an external circuit, care is required when using this mode. item previous track jump mode new track jump mode a b c a b c 1 track jump in (out) #1 233 s 233 s 60 ms 233 s 233 s 60 ms 1 track jump in (out) #2 0.5 track jump 233 s 60 ms 0.5 track jump 0.5 track jump 60 ms period period period 1 track jump in (out) #3 0.5 track jump 233 s this period does 0.5 track jump 0.5 track jump this period does period not exist. period period not exist. 1 track jump in (out) #4 0.5 track jump 233 s 60 ms; toff is low 0.5 track jump 0.5 track jump 60 ms; toff is low period during the c period. period period during the c period. 2 track jump in (out) none 1 track jump 1 track jump see note. period period 4 track jump in (out) 2 track jump 466 s 60 ms 2 track jump 2 track jump 60 ms period period period 16 track jump in (out) 9 track jump 7 track jump 60 ms 9 track jump 9 track jump 60 ms period period period period 32 track jump in (out) 18 track jump 14 track jump 60 ms 18 track jump 14 track jump 60 ms period period period period 64 track jump in (out) 36 track jump 28 track jump 60 ms 36 track jump 28 track jump 60 ms period period period period 128 track jump in (out) 72 track jump 56 track jump 60 ms 72 track jump 56 track jump 60 ms period period period period toff goes high during the period toff goes high during the period 256 track check when 256 tracks are passed over. 60 ms when 256 tracks are passed over. 60 ms the a and b pulses are not output. the a and b pulses are not output. track jump brake there are no a and b periods. 60 ms there are no a and b periods. 60 ms when the LC78625e is used in combination with an la9230/40 series lsi, since the thld signal is generated by the la9230/40, the thld pin (pin 25) will be unused, and should be left open.
no. 5502- 19 /35 LC78625e tracking brake the chart shows the relationships between the tes, hfl, and toff signals during the track jump c period. the toff signal is extracted from the hfl signal by tes signal edges. when the hfl signal is high, the pickup is over the mirror surface, and when low, the pickup is over data bits. thus braking is applied based on the toff signal being high when the pickup is moving from a mirror region to a data region and being low when the pickup is moving from a data region to a mirror region. jp three-value output the jp three value output command allows the track jump operation to be controlled from a single pin. however, the kick gain is 6 db lower when this pin is used, so applications must increase the gain in the servo system. code command res = l $b6 jp three-value output $b7 jp two-value output (earlier scheme) l l track check mode the LC78625e will count the specified number of tracks when the microprocessor sends an arbitrary binary value in the range 8 to 254 after issuing either a track check in or a track check out command. code command res = l $f0 track check in $f8 track check out $ff two-byte command reset l l
no. 5502- 20 /35 LC78625e note: * when the desired track count has been input in binary, the track check operation is started by the fall of rwc. * during a track check operation the toff pin goes high and the tracking loop is turned off. therefore, feed motor forwarding is required. * when a track check in/out command is issued the function of the wrq signal switches from the normal mode subcode q standby moni tor function to the track check monitor function. this signal goes high when the track check is half completed, and goes low when the check fin ishes. the control microprocessor should monitor this signal for a low level to determine when the track check completes. * if a two-byte reset command is not issued, the track check operation will repeat. that is, to skip over 20,000 tracks, issue a track check 201 command once, and then count the wrq signal 100 times. this will check 20,000 tracks. * after performing a track check operation, use the brake command to have the pickup lock onto the track. 9. error flag output; pin 58: eflg, pin 62: fsx the fsx signal is generated by dividing the crystal oscillator clock, and is a 7.35 khz frame synchronization signal. the error correction state for each frame is output from eflg. the playback ok/ng state can be easily determined from the extent of the high level that appears here. 10. subcode p, q, and r to w output circuit; pin 59: pw, pin 57: sbsy, pin 60: sfsy, pin 61: sbck pw is the subcode signal output pin, and all the codes, p, q, and r to w can be read out by sending eight clocks to the sbck pin within 136 s after the fall of sfsy. the signal that appears on the pw pin changes on the rising edge of sbck. if a clock is not applied to sbck, the p code will be output from pw. sfsy is a signal that is output for each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode symbol (p to w). subcode data p is output on the fall of this signal. sbsy is a signal output for each subcode block. this signal goes high for the s0 and s1 synchronization signals. the fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode block. (eiaj format)
no. 5502- 21 /35 LC78625e 11. subcode q output circuit; pin 63: wrq, pin 64: rwc, pin 65: sqout, pin 67: cqck, pin 75: cs subcode q can be read from the sqout pin by applying a clock to the cqck pin. of the eight bits in the subcode, the q signal is used for song (track) access and display. wrq will be high only if the data passed the crc error check and the subcode q format internal address is 1 (note 1). the control microprocessor can read out data from sqout in the order shown below by detecting this high level and applying cqck. when cqck is applied the dsp disables register update internally. the microprocessor should give update permission by setting rwc high briefly after reading has completed. wrq will fall to low at this time. since wrq falls to low 11.2 ms after going high, cqck must be applied during the high period. note that data is read out lsb first. note: 1. these conditions will be ignored if an address free command is sent. this is provided to handle cd-rom applications. note: normally, the wrq pin indicates the subcode q standby state. however, it is used for a different monitoring purpose in track ch eck mode and during internal braking. (see the items on track counting and internal braking for details.) the LC78625e becomes active when the cs pin is low, and subcode q data is output from the sqout pin. when the cs pin is high, t he sqout pin goes to the high-impedance state. code command res = l $09 address free $89 address 1 l l cont adr tno index (point) * min sec frame zero amin (pmin) * /pkmin asec (psec) * /pksec afra m e (pframe) * /pkframe lvm data/pkm data lvm data/pkm data *: items in parentheses refer to the read-in area. lvm/pkm 16-bit data
no. 5502- 22 /35 LC78625e 12. level meter (lvm) data and peak meter (pkm) data readout level meter (lvm) the lvm set command ($2c) sets the LC78625e to lvm mode. lvm data is a 16-bit word in which the msb indicates the l/r polarity and the low-order 15 bits are absolute value data. a one in the msb indicates left channel data and a zero indicates right channel data. lvm data is appended after the 80 bits of subcode q data, and can be read out by applying 96 clock cycles to the cqck pin. each time lvm data is read out the left/right channel state is inverted. data is held independently for both the left and right channels. in particular, the largest value that occurs between readouts for each channel is held. peak meter (pkm) the pkm set command ($2b) sets the LC78625e to pkm mode. pkm data is a 16-bit word in which the msb is always zero and the low-order 15 bits are absolute value data. this functions detects the maximum value that occurs in the data, whichever channel that value occurs in. pkm data is read out in the same manner as lvm data. however, data is not updated as a result of the readout operation. the absolute time for pkm mode subcode q data is computed by holding the absolute time (atime) detected after the maximum value occurred and sending that value. (normal operation uses relative time.) it is possible to set the LC78625e to ignore values larger than the already recorded value by issuing the pkm mask set command, even in pkm mode. this function is cleared by issuing a pkm mask reset command. (this is used in pk search in a memory track.) 13. mute control circuit an attenuation of 12 db (mute ?2 db) or full muting (mute db) can be applied by issuing the appropriate command from the table. since zero cross muting is used, there is minimal noise associated with this function. zero cross is defined for this function as the top seven bits being all ones or all zeros. 14. interpolation circuit outputting incorrect audio data that could not be corrected by the error detection and correction circuit would result in loud noises being output. to minimize this noise, the LC78625e replaces the incorrect data with linearly interpolated data based on the correct data on either side of the incorrect data. more precisely, the LC78625e uses this technique if c2 flags occurred up to three times in a row. if c2 flags occurred four or more times in a row, the LC78625e converges the output level to the muting level. however, when correct data is finally output following four or more c2 flag occurrences, the LC78625e replaces the 3 data items between the data output four items previously and the correct data with linearly interpolated data. code command res = l $2b pkm set (lvm reset) $2c lvm set (pkm reset) l l $2d pkm mask set $2e pkm mask reset l l code command res = l $01 mute 0 db $02 mute ?2 db $03 mute db l l
no. 5502- 23 /35 LC78625e code command res = l $28 sto cont l l $29 lch cont $2a rch cont code command res = l $81 att data set data 00h set $82 att 4step up (mute db) $83 att 4step down $84 att 8step up $85 att 8step down $86 att 16step up $87 att 16step down 15. bilingual function following a reset or when a stereo command ($28) has been issued, the left and right channel data is output to the left and right channels respectively. when an lch set command ($29) is issued, the left and right channels both output the left channel data. when an rch set command ($2a) is issued, the left and right channels both output the right channel data. 16. de-emphasis; pin 32: emph the pre-emphasis on/off bit in the subcode q control information is output from the emph pin. when this pin is high, the LC78625e internal de-emphasis circuit operates and the digital filters and the d/a converter output de- emphasized data. 17. digital attenuator digital attenuation can be applied to the audio data by setting the rwc pin high and inputting the corresponding two- byte command to the coin pin in synchronization with the cqck clock. attenuation setup since the attenuation level is set to the muted state (a muting of - is specified by an attenuation coefficient of 00h) after the LC78625e is reset, the attenuation coefficient must be directly set to eeh (using the att data set command) to output audio signals. note that the attenuation level can be set to one of 239 values from 00h to eeh. these two-byte commands differ from the two-byte commands used for track counting in that it is only necessary to set rwc once and a two-byte command reset is not required. (see the item on two-byte commands (rwc set once) on page 11.) after inputting the target attenuation level as a value in the range 00h to eeh, sending an attenuator step up/down command will cause the attenuation level to approach the target value in steps of 4, 8, or 16 units as specified in synchronization with rising edges on the lrsy input. however, the att data set command sets the target value directly. if a new data value is input during the transition, the value begins to approach the new target value at that point. note that the up/down distinction is significant here.
att data audio output level = 20 log [db] 100h for example, the formula below calculates the time required for the attenuation level to increase from 00h to eeh when a 4step up command is executed. note that the control microprocessor must provide enough of a time margin for this operation to complete before issuing the next attenuation level set command. 238 levels 4 steps =21.6 ms 44.1 khz (lrsy) note: * setting the attenuation level to values of efh or higher is disallowed to prevent overflows in one-bit d/a converter calculatio ns from causing noise. mute output; pin 46: mutel, pin 55: muter these pins output a high level when the attenuator coefficient is set to 00h and the data in each channel has been zero for a certain period. if data input occurs once again, these pins go low immediately. 18. digital filter outputs; pin 33: lrcko, pin 34: dforo, pin 35: dfolo, pin 36: dacko data for use with an external d/a converter is output msb first from dforo and dfolo in synchronization with the falling edge of dacko. these pins are provided so that an external d/a converter can be used if desired. although this output is from 8x oversampling filters for normal-speed playback, digital 4 oversampling filters are used in double-speed playback. no. 5502- 24 /35 LC78625e
19. one-bit d/a converter the LC78625e pwm block outputs a single data value in the range ? to +3 once every 64fs period. to reduce carrier noise, this block adopts an output format in which each data switching block is adjusted so that the pwm output level does not invert. also, the attenuator block detects 0 data and enters muting mode so that only a 0 value (a 50% duty signal) is output. this block outputs a positive phase signal to the lchp (rchp) pin and a negative phase signal to the lchn (rchn) pin. high-quality analog signals can be acquired by taking the differences of these two output pairs using external low-pass filters. the LC78625e includes built-in extraneous radiation suppression resistors (1 k ) in each of the lchp/n and rchp/n pins. pwm output format pwm output example 20. cd-rom outputs; pin 42: lrsy, pin 43: ck2, pin 44: romxa, pin 45: c2f although the LC78625e is initially setup to output audio data from the interpolation circuit msb first from the romxa pin in synchronization with the lrsy signal, the circuit can be switched to output cd-rom data by issuing a cd-rom xa command. since this data has not been processed by the interpolation, muting, and other digital circuits, it is appropriate for input to a cd-rom encoder lsi. ck2 is a 2.1168 mhz clock, and data is output on the ck2 falling edge. however, this clock polarity can be inverted by issuing a ck2 polarity inversion command. c2f is the flag information for the data in 8-bit units. note that the cd-rom xa reset command has the same function as the cont pin (pin 73). the one-bit d/a converter switches to muted mode when a cd-romxa command is input. no. 5502- 25 /35 LC78625e code command res = l $88 cd-romxa $8b cont and cd-rom xa reset l l $c9 ck2 polarity inversion LC78625e cd-rom encoder lsi (lc895xx) interface
no. 5502- 26 /35 LC78625e 21. digital output circuit; pin 56: dout this is an output pin for use with a digital audio interface. data is output in the eiaj format. this signal has been processed by the interpolation and muting circuits. this pin has a built-in driver circuit and can directly drive a transformer. ? the dout pin can be locked at the low level by issuing a dout off command. ? the ubit information in the dout data can be locked at zero by issuing a ubit off command. ? the dout data can be switched to data for which interpolation and muting processing have not been performed by issuing a cd-rom xa command. 22. antishock mode; pin 38: asdack, pin 39: asdfin, pin 40: asdepc, pin 41: adlrck, pin 42: lrsy, pin 43: ck2, pin 44: romxa, pin 45: c2f ? antishock mode is a mode in which antishock processing is applied to data that has been output once. that data can be returned and output once again as an audio playback signal. it is also possible to use only the audio playback block (the attenuator, 8x oversampling digital filter, and one-bit d/a converter circuits) and thus share the audio playback block with other systems by synchronizing the other system with this lsi's clock. note that de-emphasis on/off switching is controlled by the level applied to the asdepc pin. de-emphasis is turned on by a high level. ? the asdack (pin 38), asdfin (pin 39), asdepc (pin 40), and aslrck (pin 41) pins can be used as general- purpose ports (see page 23) if this mode is not used. ? it is possible to input the signals from the romxa (pin 44), c2f (pin 45), lrsy (pin 42), and ck2 (pin 43) pins to an antishock lsi (the sanyo lc89151) and re-input the signals output by the antishock lsi to the asdfin (pin 39), aslrck (pin 41), and asdack (pin 38) pins. these signals are then processed by the attenuator, 8x oversampling digital filter, and one-bit d/a converter circuits and output as audio signals. ? in antishock systems, the signal-processing block must operate in double-speed playback mode for data output to the antishock lsi, and the audio playback block (the attenuator, 8x oversampling digital filter, and one-bit d/a converter circuits) must operate at normal speed. this means that the control microprocessor must issue both the antic on command ($6c) as well as the df normal speed on command ($6f). ? the antic off command ($6b) clears antishock mode. code command res = l $42 dout on l l $43 dout off $40 ubit on l l $41 ubit off code command res = l $6c antic on $6b antic off l l $6f df normal speed on (only in antishock mode) $6e df normal speed off (only in antishock mode) l l
another point here is that these pins can be independently set to be used as control output pins with the port i/o set command. the ports are selected with the lower 4 bits of the one byte of data. the one byte of data corresponds to p0, p1, p2, and p3 starting with the low order bit. this command has the two-byte command format (rwc set once). one byte data + $db port i/o set dn = 1 ... sets pn to be an output pin. dn = 0 ... sets pn to be an input pin. n = 0 to 3 ports set up to be output pins can be independently set to output either a high or low level. the low order 4 bits of the one byte of data correspond to those ports. the one byte of data corresponds to p0, p1, p2, and p3 starting with the low-order bit. this command has the two-byte command format (rwc set once). one byte data + $dc port i/o set dn = 1 ... outputs a high level from pn, which is set up for output. dn = 0 ... outputs a low level from pn, which is set up for output. note that the LC78625e adds a general-purpose i/o port function that shares the asdack, asdfin, asdepc, and aslrck pins. applications that use the LC78625e with antishock mode turned on must set the p0 (asdack), p1 (asdfin), p2 (asdepc), and p3 (aslrck) pins to input mode by issuing a port i/o switching command ($db0x). but in this case,pins p0 to p3 cannot be used as input pins. in the default state following a reset, the pins p0 to p3 are set up to be input ports. the only data that can be handled by this circuit as a digital data input interface in antishock mode is data that has a 48fs bit clock rate, a 16-bit data length, an msb-first format, and a back-packed format. the figure below shows the timing. no. 5502- 27 /35 LC78625e 23. general-purpose i/o ports; pin 38: p0, pin 39: p1, pin 40: p2, pin 41: p3 when antichock mode is not used, pins 38 to 41 can be used as the general-purpose i/o ports p0 to p3. after a reset, all these pins are set up as input ports. unused ports must be either left set up as input ports and connected to 0 v or set up as output ports and left open. the port data can be read out in the order p0, p1, p2, and then p3 from the sqout pin is synchronization with falling edges on the cqck pin by issuing a port read command. this command has the one-byte command format. code command res = l $dd port read $db port i/o set port i set $dc port output
no. 5502- 28 /35 LC78625e 24. cont pin; pin 73: cont the cont pin goes high when a cont set command is issued. the clock that is used as the time base is generated by connecting a 16.9344 mhz oscillator element between these pins. the osc off command turns off both the vco and crystal oscillators. double-speed playback can be specified by microprocessor command. connect a 16.9344 mhz oscillator element between the xin (pin 77) and xout (pin 78) pins for double-speed systems. the playback speed can be set by the normal-speed playback and double-speed playback commands. recommended crystal and ceramic oscillator elements since the conditions for the load capacitors cin and cout used vary with the printed circuit board, this circuit must be tested on the printed circuit board actually used. 26. 16m and 4.2m pins; pin 71: 16m, pin 72: 4.2m in normal- and double-speed playback modes, the 16m pin buffer outputs the 16.9344 mhz external crystal oscillator 16.9344 mhz signal. the 4.2m pin supplies an la9230/40 series lsi system clock, continuously outputting a 4.2336 mhz signal. when the oscillator is turned off both these pins will be fixed at either high or low. code command res = l $0e cont set l $8b cont and cd-rom xa reset l l 25. clock oscillator; pin 77: xin, pin 78: xout code command res = l $8e osc on l l $8d osc off $ce xtal 16m l l $c2 normal-speed playback l l $c1 double-speed playback manufacturer product no. load capacitance damping resistor cin/cout (cin = cout) rd citizen watch co., ltd. csa-309 (16.9344 mhz) 6 pf to 10 pf ( 10%) 0 (crystal oscillator elements) tdk, ltd. fcr 16.93m2g (16.93 mhz) 15 pf ( 10%) 100 ( 10%) (ceramic oscillator elements) fcr 16.93mcg (16.93 mhz) 30 pf (built-in capacitor type) 47 ( 10%)
27. reset circuit; pin 68: res when power is first applied, this pin should be briefly set low and then set high. this will set the muting to db and stop the disc motor. 28. sound output function for set adjustment during manufacturing; pin 30: demo the demo pin can be used when the LC78625e is used in combination with an la9210m or la9211m. by setting this pin high, muting can be set to 0 db, the disc motor can be set to clv, and a focus start operation can be performed, even without issuing any commands from the control microprocessor. also, since the laser pin becomes active, if the mechanism and servo systems are complete, an efm signal can be acquired with only this equipment, and an audio signal can be produced without the presence of a microprocessor. however, since the digital attenuation is set to 100h, this technique is not appropriate for evaluating audio quality. no. 5502- 29 /35 LC78625e clv servo related start stop brake clv muting control 0 db ?2 db subcode q address condition address 1 address free laser control on (l) off (h) cont h l track jump mode previous new track count mode previous new digital attenuator data 0 data 00h to eeh osc on off playback speed normal speed double speed antishock mode on off digital filter normal speed on off note: setting the res pin low sets the LC78625e to the settings enclosed in boxes in the table.
no. 5502- 30 /35 LC78625e 29. other pins; pin 2:tai, pin 80: test1, pin 12: test2, pin 26: test3, pin 31: test4, pin 74: test5 these pins are used for testing the lsi's internal circuits. although the pins tai and test1 to test5 have built-in pull-down resistors, they should be connected to ground (0 v) for safety. 30. circuit block operating descriptions ram address control the LC78625e incorporates an 8-bit 2k-word ram on chip. this ram has an efm demodulated data jitter handling capacity of 4 frames implemented using address control. the LC78625e continuously checks the remaining buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine adjustments to the frequency divisor in the pck side of the clv servo circuit. if the 4 frame buffer capacity is exceeded, the LC78625e forcibly sets the write address to the 0 position. however, since the errors that occur due to this operation cannot be handled with error flag processing, the ic applies muting to the output for a 128 frame period. c1 and c2 error correction the LC78625e writes efm demodulated data to internal ram to compensate for jitter and then performs the following processing with uniform timing based on the crystal oscillator clock. first, the LC78625e performs c1 error checking and correction in the c1 block, determines the c1 flags, and writes the c1 flag register. next, the LC78625e performs c2 error checking and correction in the c2 block, determines the c2 flags, and writes data to internal ram. note: 1. if the positions of the errors determined by the c2 check agree with the those specified by the c1 flags, the correction is per formed and the flags are cleared. however, if the number of c1 flags is 7 or higher, c2 correction may fail. in this case correction is not performe d and the c1 flags are taken as the c2 flags without change. error correction is not possible if one error position agrees and the other does not. fur thermore, if the number of c1 flags is 5 or under, the c1 check result can be seen as unreliable. accordingly, the flags will be set in this cas e. cases where the number of c1 flags is 6 or more are handled in the same way, and the c1 flags are taken as the c2 flags without change. when th ere is not even one agreement between the error positions, error correction is, of course, impossible. here, if the number of c1 flags was 2 or under, data that was seen as correct after c1 correction is now seen as incorrect data. the flags are set in this case. in other cases, the c1 f lags are taken as the c2 flags without change. 2. when data is determined to have three or more errors and be uncorrectable, correction is, of course, impossible. here, if the n umber of c1 flags was 2 or under, data that was seen as correct after c1 correction is now seen as incorrect data. the flags are set in this case . in other cases the c1 flags are taken as the c2 flags without change. position divisor or handling ? or lower forcibly moves to 0 ? 589 ? 589 advancing divisors ? 589 0 588 standard divisor +1 587 +2 587 decreasing divisors +3 587 +4 or greater forcibly moves to 0 c1 check correction and flag processing no errors correction not required ?flags cleared single error correction performed ?flags cleared dual errors correction performed ?flags set three or more errors correction not possible ?flags set c2 check correction and flag processing no errors correction not required ?flags cleared single error correction performed ?flags cleared dual errors c1 flags referenced. note 1 three or more errors c1 flags referenced. note 2
command summary table blank entry: illegal command, #: command added since or changed from the lc78620/1e specifications, h : latching commands (mode setting commands), l l : commands shared with an asp (la9230m/31m or other processor), items in parentheses are asp commands (provided for reference purposes) no. 5502- 31 /35 LC78625e $00 (adj. reset) $20 h tj toff ? $40 h ubit on $60 $01 h mute 0 db $21 h tj toff ? $41 h ubit off $61 $02 h mute ?2 db $22 h new track count $42 h dout on $62 $03 h mute db $23 h old track count $43 h dout off $63 $04 h disc mtr start $24 $44 $64 $05 h disc mtr clv $25 $45 $65 $06 h disc mtr brake $26 $46 $66 $07 h disc mtr stop $27 $47 $67 $08 l l focus start #1 $28 h sto cont $48 $68 $09 h address free $29 h lch cont $49 $69 $0a h laser on $2a h rch cont $4a $6a $0b $2b h pkm set $4b $6b h antic ?ff $0c $2c h lvm set $4c $6c h antic ?n $0d $2d h pkm msk set $4d $6d $0e h cont set $2e h pkm msk reset $4e $6e h df normal speed off $0f h tracking off $2f $4f $6f h df normal speed on $10 2tj in $30 32tj in $50 $70 $11 1tj in #1 $31 1tj in #3 $51 $71 $12 1tj in #2 $32 $52 1tj in #4 $72 $13 4tj in $33 $53 $73 $14 16tj in $34 $54 $74 $15 64tj in $35 $55 $75 $16 256tc $36 $56 $76 $17 128tj in $37 $57 $77 $18 2tj out $38 32tj out $58 $78 $19 1tj out #1 $39 1tj out #3 $59 $79 $1a 1tj out #2 $3a $5a 1tj out #4 $7a $1b 4tj out $3b $5b $7b $1c 16tj out $3c $5c $7c $1d 64tj out $3d $5d $7d $1e $3e $5e $7e $1f 128tj out $3f $5f $7f continued on next page.
no. 5502- 32 /35 LC78625e $80 * $a0 h old track jmp $c0 $e0 $81 h att data set $a1 h new track jmp $c1 h double speed $e1 $82 h att 4stp up $a2 focs start #2 $c2 h normal speed $e2 $83 h att 4stp dwn $a3 h internal brke cont $c3 $e3 $84 h att 8stp up $a4 $c4 h internal brk off $e4 $85 h att 8stp dwn $a5 $c5 h internal brk on $e5 $86 h att 16stp up $a6 $c6 $e6 $87 h att 16stp dwn $a7 $c7 $e7 $88 h cdromxa $a8 h disc 8 set $c8 * $e8 $89 h address ? $a9 h disc 12 set $c9 h ck2 polarity inverted $e9 $8a h laser off $aa $ca h internal brk-dmc ? $ea $8b h cont, romxa rst $ab $cb h internal brk-dmc ? $eb $8c track jmp brk $ac * pll div off $cc h internal brk toff $ec $8d h osc off $ad * pll div on $cd h internal brk ton $ed $8e h osc on $ae $ce h xtal $ee h command noise off $8f h tracking on $af $cf * $ef h command noise on $90 ( h f. off. adj. st) $b0 h clv-ph 1/1 mode $d0 $f0 h l l track check in (2byte detect) $91 ( h f. off. adj. off) $b1 h clv-ph 1/2 mode $d1 $f1 $92 ( h t. off. adj. st) $b2 h clv-ph 1/4 mode $d2 $f2 $93 ( h t. off. adj. off) $b3 h clv-ph 1/8 mode $d3 $f3 $94 ( h lsr. on) $b4 h clv3st output on $d4 $f4 $95 ( h lsr. of/f. sv. on) $b5 h clv3st output off $d5 $f5 $96 ( h lsr. of/f. sv. of) $b6 h jp3st output on $d6 $f6 * no c period set for 2tj mode $97 ( h sp. 8cm) $b7 h jp3st output off $d7 $f7 * c period present set for 2tj mode $98 ( h sp. 12cm) $b8 $d8 $f8 h l l track check out (2byte detect) $99 ( h sp. off) $b9 $d9 $f9 $9a ( h sled. on) $ba $da $fa $9b ( h sled. off) $bb $db * port op-ed set $fb $9c ( h ef. bal. start) $bc $dc * port data set $fc $9d ( h t. servo. off) $bd $dd $fd $9e ( h t. servo. on) $be $de $fe l l nothing $9f $bf $df $ff h l l 2byte cmd rst continued from preceding page. note: $ac is a supplementary command for low-voltage operation.
sample application circuit no. 5502- 33 /35 LC78625e
differences between the LC78625e and the lc78620e no. 5502- 34 /35 LC78625e LC78625e lc78620e item content of change bilingual processing for antishock input data is now possible in antishock mode. the same bilingual control commands as those used in the lc78620e are used. (command code) (command mode) $28: stereo output (initial state after a reset) $29: both left and right are output to the left channel $2a: both left and right are output to the right channel bilingual function a bilingual processing function is not provided for antishock input data in antishock mode. the de-emphasis filters are turned on or off by the input level on the asdepc/p2 pin in antishock mode. (asdepc/p2) (de-emphasis filter) high level applied: on low level applied: off de-emphasis function the on/off state of the de-emphasis filter cannot be controlled from an external pin. a command was added that allows the presence or absence of a braking period (the c period) to be selected during two-track jumps (new track jump mode only). (command code) (c period) $f6: none (initial state after a reset) $f7: present (60 ms) track jump function there is no c period during two-track jumps (in new track jump mode). the frequency range was increased over that supported by the lc78620e. (the range is identical to that of the lc78622e) this resulted in a change in the value of the resistor used on the fr pin: 1.2 k . vco circuit a 5.1 k resistor is connected to the fr pin. addition of a supplementary command for low-voltage operation. $ac: pll divider off (low-voltage operation supplementary command) $ad: pll divider on (initial state after a reset) pll circuit no such commands are supported. when antishock mode is not used, the antishock input pins can be used as general-purpose i/o pins. to support this functionality, the pin names were changed and commands were added. (these command codes are identical to those on the lc78622e.) ?pin name changes: (LC78625e) (lc78620e) asdack/p0 ? asdack asdfin/p1 ? asdfin asdepc/p2 ? asdfir adlrck/p3 ? aslrck ?added commands: $db0x: i/o switching command (2 bytes) $dc0y: port output data setup command (2 bytes) $dd: port input command (1 byte) here x and y represent 4-bit data items that control p0, p1, p2, and p3 in order starting with the low order bit. x: a zero specifies input and a one specifies output. (these pins default to input after a reset.) y: a zero specifies a low-level output, and a one specifies a high-level output. general-purpose ports added there are no general-purpose ports.
no. 5502- 35 /35 LC78625e this catalog provides information as of february, 1997. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. cd digital signal processor lsi functional comparison type no. lc7861ne ? lc7868e ? lc78681e ? lc78620e lc7860ka lc7861ke lc7867e lc7868ke lc7869e lc78681ke lc78621e function LC78625e efm-pll when used along when used along when used along when used along when used along when used along built-in vco with an analog asp. with an analog asp. with an analog asp. with an analog asp. with an analog asp. with an analog asp. 16kram external l l l l l l l l l l l l digital outputs l l l l l l l l l l l l interpolation 2 4 4 4 4 4 4 zero cross muting l l l l l l l l l l l l level meter peak search l l l l l l l l bilingual function l l l l l l l l digital attenuator l l 2 fs l l l l 4 fs l l 8 fs l l l l digital de-emphasis l l l l l l one-bit d/a converter l l

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